The present invention relates generally to electronic circuits, and, more specifically to a method for determining power leakage of an electronic circuit.
Electronic circuits are designed using multiple digital logic elements and often are prone to power leakage. Power leakage is the power consumed by the electronic circuit due to unintended leakage of power in the digital logic elements and is used to determine a supply-ground configuration of each digital logic element, as well as power consumption and package selection of the electronic circuit. Incorrect determination of power leakage can lead to unexpected power consumption, incorrect supply-ground configuration and incorrect package selection. Incorrect supply-ground configuration further can result in improper operation of the circuit, while incorrect package selection can lead to improper heat dissipation, which affects the power characteristics of the circuit. Thus, accurate determination of power leakage is crucial for proper operation of the electronic circuit.
Several techniques are used to determine power leakage. One such technique determines the power leakage by multiplying a gate count of the circuit and a standard average power leakage value of a particular gate type, such as a NAND gate. Another method models all of the digital logic elements as p-channel and n-channel transistors and determines cumulative widths of all p-channel and n-channel transistors. Thereafter, a p-channel transistor with a width equal to the cumulative width of all the p-channel transistors and an n-channel transistor with a width equal to the cumulative width of all the n-channel transistors are simulated and the power leakage is determined.
The power leakage of a digital logic element varies considerably based on its inputs. The variation between lowest and highest power leakages of the digital logic element based on the inputs may be quite high (ranging up to ten times). However, none of the above-mentioned techniques determines the power leakage of the digital logic element based on the inputs provided to the digital logic element.
There are some other techniques that determine power leakage based on the inputs provided to the digital logic elements. In one such technique, an electronic circuit design is simulated for all possible input values corresponding to application software for which it is designed and the power leakage is determined based on the simulations. However, determining the power leakage for each possible input value of the application software is time consuming. Another method uses a probabilistic mathematical model to determine probabilities of occurrences of all possible inputs at each digital logic element, based on which the power leakage of each digital logic element is calculated. However, to determine the probabilities of occurrences of all possible inputs, the correlation between all digital logic elements needs to be known and obtaining the correlation is computationally complex and further time consuming. Statistical simulation techniques such as Monte Carlo simulation may also be used, however, these techniques require numerous simulations for accurate determination of the power leakage and are time consuming and require large amounts of memory. Yet another method simulates the electronic circuit design for a set of random test inputs. Thereafter, a feature vector representing most likely inputs of the random test inputs is generated and the power leakage values obtained. However, determining the feature vector is difficult and renders the method inefficient.
Therefore, it would be advantageous to have a system and method that accurately determines power leakage of an electronic circuit design, that is not time consuming, and that overcomes the limitations of the existing methods of determining power leakage.